Top-down fabrication of reconfigurable n

Reconfigurable FETs (RFETs) can be toggled - unlike conventional CMOS transistors - between p- and n-type behavior in runtime. This allows to create compact and delay-efficient logic gates that can switch their functionality dynamically. RFETs are based on an intrinsic semiconductor channel with Schottky junctions at source and drain and have at least two separate gates to control polarity and on/off state. Additional independent gates can enhance the versatility and switching slopes of the transistor.This thesis demonstrates the top-down fabrication and electrical characteristics of silicon-based RFETs with multiple independent gates. All processes required for forming silicon nanowires, omega-gate layout and nickel silicide contacts are described in detail. Further, the various influences of processing conditions, material stacks and geometry on the growth of nickel silicides in nanowires are examined. Lastly, the electrical characteristics of multiple RFETs with two to four individual gates are discussed and compared to those of prior-art RFET implementations.